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Assistant Professor,
Electrical Engineering
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Member,
California NanoSystems Institute
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Education: |
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Degrees:
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Ph.D., Stanford University, 2004
M.S., Hong Kong University of Science and Technology, 2001
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Contact Information:
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Box 951594
UCLA
Los Angeles, CA 90095
UNITED STATES
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Work Phone Number:
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310-267-4786
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Technical Research Interest:
My research group (http://www.ee.ucla.edu/~chui/) focuses on developing
nanostructure devices and technology for the next generation energy efficient, fault
tolerant, and high performance integrated circuits and systems. Below are two
sample, funded multi-disciplinary research projects that my group is actively pursing.
Nanotechnolgy Enabled Fault Tolerant Computing
Nanoscale Application Specific IC (NASIC) based processor with a variety of
built-in fault tolerance techniques has been pioneered by our collaborator, who is a
renowned computer architect. This novel nano-architecture has been theoretically
shown to outperform conventional CMOS and my group is developing the enabling
nanotechnology to fabricate the tile-based 2D semiconductor nanowire grid fabrics
and cross-point transistors. In particular, we are tackling the fundamental problem of
nanowire or nanotube alignment with an intrinsic control of the nanowire or
nanotube pitch by fusing the ‘bottom-up’ and ‘top-down’ approaches. This project
combines knowledge from chemistry for nanowire self-assembly and semiconductor
nanofabrication for sub-lithographic nanostructure formation.
Graphene Nanostructure Devices and Technology
Graphene has many fascinating yet unique physical and electronic properties.
For instance, it is a semi-metal with an almost zero bandgap at room temperature
that possesses extremely high electron mobility. These characteristics could enable
devices with high transconductance, intrinsic gain, and cut-off frequencies at low
supply voltage for receiver front-end applications. My group is developing the
nanofabrication technology in demonstrating a revolutionary RF transistor with
graphene channel. Working with in-house synthetic chemist and material scientist,
who are existing CNSI members, my group focuses on the modular process
developments such as graphene patterning, passivation, and contact formation.
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P. T. Chen, Y. Sun, E. Kim, P. C. McIntyre, W. Tsai, M. Garner, P. Pianetta, Y. Nishi,
and C. O. Chui, HfO2 Gate Dielectric on (NH4)2S Passivated (100) GaAs Grown by Atomic Layer Deposition, Journal of Applied Physics, 2008, 103 (3), 034106.
K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. M.
Heyns, T. Krishnamohan, K. C. Saraswat, H. E. Maes, and G. Groeseneken, On the Correct Extraction of Interface Trap Density of MOS Devices with High-Mobility Semiconductor Substrates, IEEE Transactions on Electron Devices, 2008, 55 (2), 547-556.
N. Goel, P. Majhi, C. O. Chui, W. Tsai, D. Choi, and J. S. Harris, InGaAs Metal- Oxide-Semiconductor Capacitors with HfO2 Gate Dielectric Grown by Atomic-Layer Deposition, Applied Physical Letters, 2006, 89 (16), 163517.
A. K. Okyay, C. O. Chui, and K. C. Sarawat, Leakage Suppression by Asymmetric Area Electrodes in Metal-Semiconductor-Metal Photodetectors, Applied Physical Letters, 2006, 88 (6), 063505.
H. Lan, T. W. Chen, C. O. Chui, P. Nikaeen, J. W. Kim, and R. W. Dutton, Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs, IEEE J. of Solid-State Circuits (Special Issue on the IEEE 2005 Custom Integr. Circuit Conf.), 2006, 41 (8), 1817-1829.
C. O. Chui, D.-I. Lee, A. A. Singh, P. A. Pianetta, and K. C. Saraswat,, Zirconia-germanium interface photoemission spectroscopy using synchrotron radiation , Journal of Applied Physics , 2005, 97 (11), 113518.
C.-H. Lu, G. M. T. Wong, M. D. Deal, W. Tsai, P. Majhi, C. O. Chui, M. R. Visokay, J.
J. Chambers, L. Colombo, B. M. Clemens, and Y. Nishi,, Characteristics and Mechanism of Tunable Work Function Gate Electrodes Using a Bilayer Metal Structure on SiO2 and HfO2,, IEEE Electron Device Letters, 2005, 26 (7), 445-447.
A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, Fabrication of High-Quality p-MOSFET in Ge Grown Heteroepitaxially on Si, IEEE Electron Device Letters, 2005, 26 (5), 311-313.
C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. Saraswat, Germanium n-type Shallow Junction Activation Dependences, Applied Physical Letters, 2005, 87 (9).
A. Nayfeh, C. O. Chui, K. C. Saraswat, T. Yonehara,, Effects of Hydrogen Annealing on Heteroepitaxial-Ge Layers on Si: Surface Roughness and Electrical Quality, Applied Physical Letters, 2004, 85 (14), 2815-2817.
H. Kim, P. C. McIntyre, C. O. Chui, K. C. Saraswat, and M.-H. Cho, Interfacial Characteristics of HfO2 Grown on Nitrided Ge (100) Substrates by Atomic-Layer Deposition, Applied Physical Letters, 2004, 85 (14), 2902-2904.
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